1. Field of the Invention
This invention relates to a combination of field effect transistors (FETs) connected to a transferred electron logic device (TELD) to form an exclusive OR gate. The TELD includes an output electrode capacitively coupled thereto for transmission of an output of predetermined voltage and alternating polarity for use in directly interconnected cascaded high speed logic applications.
2. DESCRIPTION OF THE PRIOR ART
In signal and data processing applications at gigabit rates it is desirable to utilize devices which offer fast switching speeds, typically on the order of 20 to 50 pico-seconds and output signals of substantial gains while providing "fan-out." "Fan-out" as the term is commonly used on logic applications refers to the number of similar circuits or gates a device is capable of driving. In many applications, it is also desirable to cascade the devices to meet various circuit requirements. In the cascaded arrangement, the output of the first device must be capable of triggering the following device. If the output of a logic device is of the same polarity as the input of the device to which it is connected triggering can be effected without additional inverters after each stage facilitating small or medium scale integration.
Logic gates formed of gallium arsenide (GaAs) field effect transistors operating in the depletion mode or formed of GaAs TELDs can handle data rates that are substantially higher than the highest rates that appear possible with logic gates made from silicon. Transferred electron logic devices, also at times referred to as Gunn devices, have desirable threshold properties which are utilized to achieve pulse rise and delay times of less than 50 pico-seconds. TELD logic gates can also be directly interconnected without inverters or level shifters. However, the TELD logic gate not only has poor input sensitivity but is also technologically difficult to design for high stable gain. Input sensitivity of a TELD, as is known in this art, is the minimum voltage signal required to trigger the TELD into the threshold mode of operation causing the formation of domains in the device and dropping the current therethrough. In contrast with a TELD, a FET has good sensitivity and easily achievable high gain, but such devices cannot be directly interconnected because the required dc input and available dc output levels are different. Moreover, the minimum pulse width that can be processed through FET circuits is disadvantageously in the order of 400 pico-seconds as discussed in Gunn Effect Logic Devices, by Hans L. Hartnagel, published by American Elsevier, Co., Inc., N.Y., 1973 page 111.
A circuit containing a pair of FETs and a pair of TELDs arranged as an exclusive-OR is known. In the known exclusive-OR circuit the FETs are connected source to source. A load resistor in series with the sources is used to produce the output signal. Respective drains are connected to two separate TELDs. The respective gates are coupled to input terminals to receive signals, the exclusive-OR product of which is to be determined. The TELDs are normally biased below threshold. The circuit component values are selected such that if a signal is applied to only one FET, oscillation is initialed, but if signals are applied to both FETs, oscillation in the TELD is not initialed. In this circuit the change in output voltage is a function of the load resistor value and current therethrough. The value of the resistor must be kept low to allow high speed operation. Therefore, for a reasonable output voltage change, the current must be relatively high.